1. Field of the Invention
The present invention relates to a method for fabricating a structure in a semiconductor device and, more particularly, to a plural wells structure in a semiconductor device suitable for achieving high integration, and a method for forming the same.
2. Discussion of the Related Art
In order to improve the performance of a semiconductor device, impurity ions of a conductivity type opposite to that of a substrate are first implanted into the substrate and then wells are formed.
There are various types of wells. Single well or twin well is formed by selectively or entirely implanting and diffusing ions before performing a device-isolating process. As for a diffused well, triple wells are formed. As for a retrograde well, after performing a device-isolating process, wells of different types are formed by adjusting energy of ion-implantation. A retrograde well may have a buried implanted layer for lateral isolation (BILLI) structure.
Among the aforementioned wells, a diffused well will be described. A single well or twin wells can be made to have a desired depth by controlled diffusion, which is performed vertically and horizontally. It is difficult to adjust the profile of the well. Also, the process tolerance is not tight enough.
For these reasons, triple wells are preferred to a signal well or twin wells. Nevertheless, the process for forming triple wells is complicated, making the productivity inferior. Thus, development and research has been directed to improving the productivity by simplifying the process.
A conventional method for forming wells of a semiconductor device will be described below with reference to the accompanying drawings.
FIGS. 1a to 1d are cross-sectional views showing steps of a method for forming wells of a semiconductor device. Conventional triple wells are composed of a p-type well surrounded by an n-type shield region on a cell region, and an n-type well and a p-type well for forming a CMOSFET. The triple wells isolate the p-type well in the cell region from the p-type well in a periphery region.
Referring initially to FIG. 1A, a buffer oxide layer 2 is deposited on a semiconductor substrate 1 and a 4 .mu.m thick special photo resist film 3 is coated on the entire surface and patterned on a predetermined area by an exposure and development process. With the photo resist pattern 3 serving as a mask, n-type impurity ions are implanted to form an n-type shield region 4 at a predetermined depth below the surface of the semiconductor substrate 1.
Referring to FIG. 1B, the remaining photo resist film 3 is removed and another photo resist film 5 is coated on the entire surface, patterned by an exposure and development process and accordingly removed over a periphery portion of the n-type shield region 4 in the cell region and over a predetermined area of a periphery region, as well. With the photo resist pattern 5 serving as a mask, n-type impurity ions are implanted to form an n-type shield sidewall 6a on the periphery portion of the n-type shield region 4 in the cell region and an n-type well 6b in the periphery region. At this time, the n-type shield sidewall 6a is spaced apart from the n-type well 6b.
Referring to FIG. 1C, the remaining photo resist film 5 is removed. Then another photo resist film 7 is coated on the entire surface and patterned by an exposure and development process and accordingly removed over the n-type shield region 4 inside the n-type shield sidewall 6a and on a portion of the n-type well 6b. With the photo resist pattern 7 serving as a mask, p-type impurity ions are implanted into the semiconductor substrate 1. Thus, there are formed a first p-type well 8a in the semiconductor substrate 1 on the n-type shield region 4 and inside the n-type shield sidewall 6a and a second p-type well 8b in the semiconductor substrate 1 adjacent to the n-type well 6b.
Referring finally to FIG. 1D, the remaining photo resist film 7 is removed, thereby completing the whole process steps of forming triple wells.
The conventional method for forming wells of a semiconductor device has the following problems. First of all, mask processes are required three times and thus corresponding patterning processes and cleaning processes are also required. Three mask processes complicate the overall process and reduce the productivity. In addition, since an n-type shield region is formed deeply beneath the surface of a semiconductor substrate by high energy ion implantation, a 4 .mu.m thick special photo resist film is required. This further complicates the process.